Click any coloured block in the block diagram to highlight it and read its description. The corresponding register on the right panel scrolls into view and is outlined in blue.
Each register shows all 8 bits with their names and current values. Use the dropdown menus below each register to change bit fields. The hex value updates instantly.
WGM0[2:0] spans two registers. Set WGM0[1:0] in TCCR0A and WGM02 in TCCR0B together to pick the mode:
| WGM[2:0] | Mode | TOP |
|---|---|---|
| 000 | Normal | 0xFF |
| 001 | Phase-correct PWM | 0xFF |
| 010 | CTC | OCR0A |
| 011 | Fast PWM | 0xFF |
| 101 | Phase-correct PWM | OCR0A |
| 111 | Fast PWM | OCR0A |
Controls how fast the counter ticks relative to clkIO (16 MHz). A higher prescaler gives a lower output frequency and longer period.
| CS0[2:0] | Divisor | Tick period |
|---|---|---|
| 001 | /1 | 62.5 ns |
| 010 | /8 | 500 ns |
| 011 | /64 | 4 us |
| 100 | /256 | 16 us |
| 101 | /1024 | 64 us |
These 8-bit registers set the compare thresholds. In Fast PWM and Phase-correct PWM modes, the duty cycle of OC0A is OCR0A/TOP and OC0B is OCR0B/TOP. In CTC mode, OCR0A defines the TOP value and therefore the output frequency.
Controls what happens to the OC0A (PD6) and OC0B (PD5) output pins on a compare match. Set to 00 to disconnect, 10 for non-inverting PWM (clear on match, set at BOTTOM), or 11 for inverting PWM.
Enable up to three interrupt sources. TOIE0 fires on counter overflow (TOV0 flag). OCIE0A fires when TCNT0 matches OCR0A (OCF0A flag). OCIE0B fires when TCNT0 matches OCR0B (OCF0B flag). Flags are in TIFR0 and cleared by writing 1.
TCNT0 shows the raw counter ramp. Dashed lines mark the OCR0A and OCR0B compare levels. OC0A and OC0B show the waveform output pins. TOVn pulses high at each overflow event.
Fast PWM: f = clkIO / (N x (TOP + 1))
CTC: f = clkIO / (2 x N x (OCR0A + 1))
Phase-correct: f = clkIO / (2 x N x TOP)
where N = prescaler divisor, clkIO = 16 MHz